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Physical Design Engineer, Lead

4 weeks ago

Hyderabad City Taluka, Pakistan Qualcomm Technologies, Inc Full time
Company: Qualcomm India Private Limited
Job Area: Engineering Group, Hardware Engineering
General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. Qualcomm Hardware Engineers plan, design, optimize, verify, and test electronic systems, including bring-up yield, circuits, mechanical systems, digital/analog/RF/optical systems, equipment and packaging, test systems, FPGA, and DSP systems, launching cutting-edge products. They collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:
  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 3+ years of experience.
  • OR Master's degree with 2+ years of experience.
  • OR PhD with 1+ year of experience.
We seek bright ASIC design engineers with excellent analytical and technical skills, responsible for delivering Snapdragon CPU designs for high-performance SoCs in sub-10nm processes for mobile, compute, and IoT markets.
Responsibilities include:
  • Participate in ASIC development projects focusing on Place and Route, Timing Closure, Low Power, Power Analysis, and Physical Verification.
  • Create design experiments, conduct detailed PPA analysis, and tune recipes for project improvements.
  • Collaborate with RTL design, synthesis, low power, thermal, and power analysis teams to optimize performance, power, and area.
  • Develop Place & Route recipes for optimal PPA.
Minimum Qualifications:
  • 7+ years of experience in high-performance core Place & Route and ASIC implementation.
Preferred Qualifications:
  • Extensive experience with FC or Innovus tools.
  • Complete ASIC flow expertise, including low power, performance, and area optimization.
  • Experience with STA tools like PrimeTime or Tempus.
  • Proficiency in constraint generation and validation.
  • Experience with multiple power domains and UPF/CPF definitions.
  • Formal verification experience (Formality/Conformal).
  • Skills in Perl/Tcl, Python, C++.
  • Strong problem-solving and debugging skills in ASIC development.
  • Knowledge of CPU micro-architecture and critical path analysis.
  • Experience with low power and high-speed CPU implementation techniques.
  • Clock Tree Implementation expertise for high-speed designs.
  • Exposure to constraint management tools and Verilog coding.
Education Requirements:

Qualcomm is an equal opportunity employer. For accommodations during the application process, contact disability-accomodations@qualcomm.com. Qualcomm is committed to accessible hiring processes and workplaces for individuals with disabilities.

Additional Information:

Qualcomm expects employees to adhere to all applicable policies, including security and confidentiality requirements. Unsolicited resumes from staffing agencies are not accepted, and Qualcomm is not responsible for fees related to such submissions.

Contact:

For more information about this role, please contact Qualcomm Careers.

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