
SOC Design Verification Staff Engineer
1 week ago
Job Area: Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a DV Engineer focusing on SOC design verification, you will understand the internal requirements of complex auto, compute, mobile, XR-VR, IoT SOCs and develop verification strategies. You will establish methodologies, develop test plans, and verify that designs meet high-quality standards. Early involvement in DV will also include participation in architecture and product definition throughout the product lifecycle.
Preferred Qualifications- B.E/B.Tech/M.E/M.Tech in Electronics with 5+ years in verification.
- Strong fundamentals in digital ASIC verification.
- Experience in IP/SS/SoC level verification of medium to high complexity designs.
- Familiarity with system-level HW and SW debug techniques and verification requirements.
- Understanding of the complete verification lifecycle (test plan, testbench, coverage).
- Proficiency in SystemVerilog/UVM, assertions, and coverage-based verification.
- Experience with PSS or higher-level test construction languages is an advantage.
- Knowledge of Interconnect architecture and protocols like AMBA - ACE/CHI/AXI.
- Understanding of low power design techniques and constructs.
- Experience with UPF/CPF power-aware verification.
- Knowledge of scripting languages such as Perl, Python; GLS is a plus.
- Experience with NoC/Interconnects verification, Bus protocols, Coherency, Performance, Latency, clock gating.
- Knowledge of multimedia blocks (Display, Camera, Video, GFx) or peripheral blocks (PCIe, USB, UFS, I3C).
Bachelor's degree in relevant fields with 3+ years of experience, or a master's degree with 2+ years, or a PhD with 1+ year.
Roles and Responsibilities:- Define verification architecture, develop test plans, and build environments.
- Collaborate with design teams to understand design intent and verification schedules.
- Verify subsystems and full SoC using advanced methodologies.
- Create agents and checkers, develop test plans based on architecture specs or standards.
- Verify low power aspects across all modes using RTL, PA-RTL, PA-GLS, and Formal.
- Manage end-to-end DV tasks, including coding test benches, assertions, debugging, and coverage.
- Assist in silicon bring-up and debugging activities.
Bachelor's degree with 4+ years, master's with 3+, or PhD with 2+ years of relevant experience.
Note:Qualcomm is an equal opportunity employer. For accommodations, contact disability-accommodations@qualcomm.com. We are committed to accessible hiring processes and workplaces.
Qualcomm expects employees to adhere to all policies regarding confidentiality and security.
For staffing agencies: Our careers site is for individual applicants only. Unsolicited resumes from agencies will not be accepted, and we do not pay fees for such submissions.
Contact:For more information, contact Qualcomm Careers.
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