SOC Verification Engineer for Complex Designs

3 days ago

Hyderabad City Taluka, Pakistan beBee Careers Full time
Job Title: SOC Verification Engineer for Complex Designs

As a highly skilled Digital Verification (DV) Engineer with a focus on System-on-Chip (SOC) design verification, you will play a crucial role in understanding the intricate requirements and complexities of our cutting-edge auto, compute, mobile, XR-VR, IoT SOCs. Your expertise will be essential in architecting the required verification strategy, setting up methodologies, developing test plans, and verifying that the design meets the highest quality standards.

About the Role:

In this position, you will have early involvement in the product life-cycle, participating in architecture/product definition from the start. Your strong fundamentals in digital ASIC verification will enable you to tackle medium to high complexity designs at the IP/SS/SoC level. You will be responsible for defining verification architecture, developing test plans, and working closely with design teams to understand design intent and bring up verification plans and schedules.

Key Responsibilities:
  • Developing and implementing advanced verification methodologies for Subsystems and Full SoC
  • Designing and building agents and checkers from scratch, as well as writing test plans from design architecture specs and/or protocol standards
  • Owning end-to-end DV tasks, including coding Test benches and test cases, writing assertions, debugging UPF and RTL, and achieving all coverage goals
  • Assisting in silicon bring-up, debug, and bring-up activities
Requirements:
  • B.E/B.Tech/M.E/M.Tech in Electronics with 5+ years of experience in the verification domain
  • Strong knowledge of system-level HW and SW Debug techniques and Verification requirements
  • A good understanding of the complete verification life cycle, from test plan to coverage closure
  • Proficient in System Verilog/UVM based verification skills and experience with Assertion & coverage-based verification methodology
  • Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI
  • Good understanding of low power design techniques and proficiency with low power SoC design constructs such as clock gates, level shifters, isolation cells, and state retention cells
  • Experience with UPF/CPF based power aware verification and working knowledge of GLS, PAGLS, and scripting languages like Perl, Python
  • Prior work on NoC/Interconnects end-to-end verification with solid understanding of Bus protocols, Coherency, Performance, Latency, clock gating, etc.
  • Knowledge of one or more multimedia design blocks such as Display/Camera/Video/GFx and peripheral blocks verification such as PCIe/USB/UFS/I3C

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