Senior Verification Engineer

4 days ago

Hyderabad City Taluka, Pakistan beBeeVerification Full time

Job Title:

Senior Verification Engineer

About the Role:

We are seeking an experienced Senior Verification Engineer to join our team. As a DV Engineer with a focus on SOC design verification, you will work to understand the internal requirements and complexities of highly complex auto, compute, mobile, XR-VR, IoT SOCs.

You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle.

Responsibilities:

  • Define verification architecture, develop test plans, and build verification environment
  • Work with design team to understand design intent and bring up verification plans and schedules
  • Verify Subsystems and Full SoC using advanced verification methodologies
  • Build agents and checkers from scratch
  • Develop test plan to verify all low power aspects across all modes of verification – RTL, PA-RTL, PA-GLS and Formal
  • Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals

Requirements:

  1. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience
  2. Strong fundamentals in digital ASIC verification
  3. Experience in IP/SS/SoC level verification of medium to high complexity design
  4. Familiarity with system level HW and SW Debug techniques and Verification requirements
  5. A good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
  6. Strong System Verilog/UVM based verification skills & Experience with Assertion & coverage-based verification methodology
  7. Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI
  8. Good understanding of low power design techniques
  9. Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells
  10. Experience with UPF/CPF based power aware verification
  11. Working knowledge of GLS, PAGLS and scripting languages such as Perl, Python is a plus
  12. Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc
  13. Knowledge of one or more of Multimedia design blocks such as Display/Camera/Video/GFx
  14. Knowledge of one or more of peripheral blocks verification such as PCIe/USB/UFS/I3C

Preferred Qualifications:

  1. Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience

Note:

Please note that Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law

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