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2 days ago
You will be responsible for improving existing methodologies and flows, reducing the number of timing signoff corners by merging different timing modes, and ensuring clock structure and debug analysis from a design perspective.
This is an excellent opportunity to apply your skills and knowledge in a dynamic environment, working closely with experienced engineers and cross-functional teams to deliver high-quality results.
Our ideal candidate will have a strong background in hardware engineering, with experience in timing closure, signoff, and backend-related methodologies and tools.
Key Skills and Qualifications- 4-10 years of experience in timing closure and signoff.
- Thorough knowledge of timing corners/modes, process variations, and signal integrity related issues.
- Expertise in STA tools (Primetime/Tempus) and flow.
- Proficient in scripting languages (TCL, PERL, PYTHON).
- Familiarity with backend related methodology and tools.
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