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4 days ago
Create efficient digital circuits using cutting-edge technologies. 3+ years of experience in logic equivalence checking, scripting, and netlist timing signoff. Familiar with Synthesis tools (Fusion Compiler/Genus) and LEC, LP signoff tools.
Proficient in VLSI front end design steps - Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking. Required skills include proficiency in Python/Tcl and standard software engineering practices like Version Control, Configuration Management, Regression is a plus.
This role requires sincerity, dedication, and a willingness to take up new challenges.
Requirements:- Experience in logic equivalence checking, scripting, and netlist timing signoff
- Familiar with Synthesis tools (Fusion Compiler/Genus) and LEC, LP signoff tools
- Proficient in VLSI front end design steps - Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking
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