Top Verification Engineer Position Available

1 day ago

Lahore, Punjab, Pakistan beBeeVerification Full time 900,000 - 1,200,000

Our company is seeking a highly skilled Design Verification Engineer to join our team. In this role, you will work closely with the designers and verification team on complex IP design verification.

The ideal candidate will have a strong background in computer science or electrical engineering, with a minimum of 4 years of experience in verification methodologies and testplan development.

This is an exciting opportunity to work with an experienced and highly motivated team of verification engineers.

Key Responsibilities:
  • Developing and executing testplans for complex IPs
  • Collaborate with the design and verification teams to ensure comprehensive coverage.
  • Utilize advanced verification methodologies to identify and resolve design issues.
  • Contribute to the continuous improvement of verification processes and methodologies.
  • Participate in code reviews and provide feedback on verification-related aspects.
  • Maintain thorough documentation of verification activities and results.
  • Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field
Mandatory Skills:
  • RISC V assembly language and C language expertise for low level programming
  • Hands on experience with RISC V Priv/Unpriv architecture is must
  • Good understanding computer architecture concepts
  • Experience with hypervisors and virtualization is add plus
  • Experience with testplan development and implementation
  • Knowledge of Verilog/System Verilog
  • Familiarity with industry-standard verification tools
  • Ability to work in a fast-paced and collaborative environment
  • Strong communication and collaboration abilities
  • Excellent problem-solving skills and attention to detail.
Desired Skills:
  • Expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM).
  • Proficiency in testbench development and verification methodologies.
  • Strong understanding of the verification life cycle.
  • Good understanding of advance computer architecture concepts such as Branch predication, out-of-order processors, cache coherency, memory consistency models
  • Contributions to RISC-V open-source projects such as arch-test development
Interested candidates should possess the following qualifications:
  • Education: Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field
  • Experience: Minimum of 4 years of experience in verification methodologies and testplan development
  • Skills: RISC V assembly language and C language expertise, good understanding of computer architecture concepts, and experience with hypervisors and virtualization

We are an equal opportunities employer and welcome applications from all qualified candidates.

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