Physical Design Engineer

4 days ago

Islamabad, Islamabad, Pakistan Dreambig Semiconductor Full time
Physical Design Engineer
Dreambig Semiconductor, Pakistan

Bachelor's/master's degree in electrical engineering, Computer Engineering, or a related field.

We are seeking a highly skilled and motivated Physical Design Engineer to join our team. As a key contributor, you will play a pivotal role in the design and implementation of our chiplet platform. You will collaborate closely with cross-functional teams to drive the physical design process and ensure the successful integration of compute, accelerator, memory, and IO chiplets into a unified, high-performance system-in-package.

Responsibilities:

  • Manage various Physical design tasks, including Placement, Timing Optimization, Clock Tree Synthesis, and Routing.
  • Engage in Chip/Block Level Floorplanning and pin assignment.
  • Conduct pre-layout Static Timing Analysis (STA) to assess feasibility, validate timing constraints, and provide feedback to design teams.
  • Review top-level/block-level clock specifications for completeness and feasibility.
  • Execute signoff tasks such as RC Extraction, Static Timing Analysis, IR drop analysis, and Physical Verification.
  • Lead the physical design team to achieve aggressive performance, power, and area (PPA) goals within tight project schedules.
  • Coordinate discussions with ASIC and design teams to ensure seamless collaboration and communication.
Job Specification

Qualifications:

  • Education: Bachelor's/master's degree in electrical engineering, Computer Engineering, or a related field.
  • Experience: Minimum of 2 years of industry experience in physical design for ASICs or SoCs.
  • Expertise: Proficiency in physical design tools (Cadence, Synopsys, etc.) and methodologies. Experience with chiplet-based design, die-to-die interfaces, and networking technologies is highly desirable.
  • Problem-solving Skills: Strong analytical and problem-solving abilities with a focus on delivering high-quality designs within project timelines.
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