SOC Design Verification Specialist

7 days ago

Hyderabad City Taluka, Pakistan beBee Careers Full time

Job Title:

SOC Design Verification Staff Engineer

Responsibilities and Expectations

We are seeking a highly skilled SOC Design Verification Staff Engineer to join our team. As a key member of the engineering group, you will be responsible for developing and executing verification strategies for complex SOCs.

You will establish methodologies, develop test plans, and verify that designs meet high-quality standards. Early involvement in DV will also include participation in architecture and product definition throughout the product lifecycle.

The ideal candidate will have a strong understanding of digital ASIC verification, experience with system-level HW and SW debug techniques, and proficiency in SystemVerilog/UVM, assertions, and coverage-based verification.

Familiarity with interconnect architecture, protocols like AMBA - ACE/CHI/AXI, and low power design techniques is also essential.

You will collaborate with design teams to understand design intent and verification schedules, create agents and checkers, and develop test plans based on architecture specs or standards.

In this role, you will manage end-to-end DV tasks, including coding test benches, assertions, debugging, and coverage, as well as assist in silicon bring-up and debugging activities.

Requirements and Qualifications

To be successful in this position, you will need a Bachelor's degree in relevant fields with 3+ years of experience, or a master's degree with 2+ years, or a PhD with 1+ year.

  • Required Skills and Experience:
  • B.E/B.Tech/M.E/M.Tech in Electronics with 5+ years in verification.
  • Strong fundamentals in digital ASIC verification.
  • Experience in IP/SS/SoC level verification of medium to high complexity designs.
  • Familiarity with system-level HW and SW debug techniques and verification requirements.
  • Understanding of the complete verification lifecycle (test plan, testbench, coverage).
  • Proficiency in SystemVerilog/UVM, assertions, and coverage-based verification.
  • Experience with PSS or higher-level test construction languages is an advantage.
  • Knowledge of Interconnect architecture and protocols like AMBA - ACE/CHI/AXI.
  • Understanding of low power design techniques and constructs.
  • Experience with UPF/CPF power-aware verification.
  • Knowledge of scripting languages such as Perl, Python; GLS is a plus.
About This Role

This is a fantastic opportunity to work on cutting-edge technologies and contribute to the development of innovative products.

If you are passionate about SOC design verification and want to join a dynamic team of engineers, please apply now.

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