Senior ASIC Design Engineer

5 days ago


Hyderabad City Taluka, Pakistan Qualcomm Technologies, Inc Full time
Responsibilities

The ideal candidate will have a strong background in constraint analysis and debug, as well as experience in reducing the number of timing signoff corners by merging different timing modes.

They will also be responsible for:

  • Developing and maintaining expert-level knowledge of ASIC design timing closure flows and methodologies.
  • Collaborating with cross-functional teams to develop solutions and meet performance requirements.
  • Analyzing and debugging timing/SDC constraints.
  • Maintaining and updating knowledge of STA tools (Primetime/Tempus) and flow.

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