Multiple Positions

Disclaimer: Only candidates with 3+ years of relevant experience will be considered. Fresh graduates and junior-level applicants will not be entertained for this position.

Location: Karachi, Islamabad, Lahore (on-site)

Please send CVs to

Mention the position in the subject line.

Referrals are highly appreciated — thank you in advance for your support

Senior Embedded Software

Qualifications:

• Bachelor's degree in electrical engineering, Electronics, or Computer Science.
• 2 to 3 years of hands-on experience.

Experience & Skills:

• Preferable experience in C language. (Must)
• Strong concepts of operating systems (Linux Kernel knowledge and RTOS concepts preferred).
• Understanding of computer architecture, including microcontrollers and microprocessors.
• Knowledge of network stack (TCP/IP), tunneling, and virtualization.
• Experience in embedded system design and development.
• Familiarity with version control tools like Git, project management tools like JIRA, and CI/CD processes.
• Strong debugging and troubleshooting skills.

Hardware Engineer

Qualifications

• At least 2-5 years of experience in FPGA design/development using HDL (Verilog/System Verilog/VHDL). (Mandatory)
• Hands-on experience on Xilinx FPGAs with Vivado IDE or similar tools.
• Experience with at least any one of the scripting languages Perl, Python, Tcl, or Shell scripting.
• Good communication and interpersonal skills.
• Familiarity with Ethernet/Network protocols would be a plus. (Mandatory)
• Familiarity with Simulations on Modelsim/Questaism would be a plus.
• Hand-on working experience with PCIe would be an added advantage.
• Experience with design verification with UVM would be an added advantage.

Key Responsibilities

• Execute end-to-end physical design tasks, including placement, timing optimization, clock tree synthesis (CTS), and routing.
• Perform synthesis, chip/block-level floorplanning, and pin assignments.
• Conduct pre-layout STA to ensure timing feasibility and constraint validation.
• Review clock specifications at the block and top levels to ensure design completeness.
• Perform signoff tasks, including RC extraction, STA, IR drop analysis, and physical verification.
• Lead PPA (Power, Performance, Area) optimization efforts to meet aggressive project timelines.
• Collaborate with ASIC and design teams to ensure seamless integration.

Physical Design Engineer

Key Skills & Expertise (Mandatory)

Physical Design (RTL to GDS)

Synthesis, Floorplanning, Placement & Routing

Static Timing Analysis (STA)

TSMC process technologies

GDS generation & signoff

Requirements

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.
• 2-5+ years of experience in ASIC physical design.
• Strong knowledge of digital tapeout processes and advanced nodes.
• Hands-on experience with industry-standard EDA tools (Cadence, Synopsys, etc.).
• Expertise in IR drop analysis, physical verification, and debugging layout issues.
• Proficiency in Verilog HDL, scripting (Perl/Tcl/Python), and physical design libraries.
• Strong problem-solving and analytical skills.
• Excellent communication and teamwork abilities.

Senior Verification Engineer

Key Responsibilities:

Design Responsibilities:

• Extract design requirements from specifications and translate them into architecture, micro-architecture, and RTL design.
• Develop and optimize RTL (Register Transfer Level) designs in Verilog/SystemVerilog for ASIC/FPGA-based projects.
• Perform unit-level testing on the RTL function and support the verification team by writing self-checking tests.
• Work closely with the physical design team to support design integration activities, including linting, CDC, SDC, synthesis, and ECOs.
• Collaborate on timing constraints, STA, back annotation of parasitics, gate-level simulations, and equivalence checking.
• Perform FPGA emulation and prototyping where required.
• Support low-power design methodologies to optimize performance and power efficiency.

Verification Responsibilities:

• Work closely with the verification team to review specifications, understand SoC/Core architecture, and define test plans, methodology, and test benches.
• Create and execute verification plans based on design specifications.
• Develop UVM-based testbenches and implement directed/random test strategies.
• Apply constrained random verification methodologies and ensure functional coverage and code coverage.
• Debug and resolve issues at simulation and emulation levels.
• Perform formal verification and functional equivalence checking.

Required Skills & Qualifications:

• B.S. or M.S. in Electrical, Electronics, Computer Engineering, or Computer Science.
• 2-5+ years of experience in digital design, RTL coding in Verilog/SystemVerilog, and functional verification.
• Strong knowledge of CPU architectures (RISC-V, ARM), IP/subsystems, interconnects, and industry-standard interfaces (AMBA, Tile Link, NoCs, etc.).
• Understanding of digital design flow, including RTL simulation, logic synthesis, timing constraints (SDC), STA, and power optimization.
• Hands-on experience in EDA tools for simulation, synthesis, and verification (Cadence, Synopsys, Mentor Graphics, or equivalent).
• Experience in writing scripts using Python, Perl, Tcl, or Shell scripting for automation.
• Familiarity with FPGA-based prototyping and low-level system programming in C/C++/assembly is a plus.
• Strong problem-solving and analytical skills.
• Excellent oral and written communication skills in English.
• Strong interpersonal skills and the desire to take on diverse challenges.

What we offer:

In-patient and OPD medical of family.

Provident fund.

Performance-based very handsome yearly raise.

Opportunity to move to the USA based on a company-sponsored H1B.

• Job Type:
  Full-time

Please note must have good CGPA

Drop Resume to

Location: Karachi, Lahore, Islamabad

Timings: 9 am to 6 pm

Working Days: Monday to Friday