FPGA Hardware/Software Engineer

2 weeks ago

Islamabad, Islamabad, Pakistan Inphoenix Pvt. Ltd. Full time 1,200,000 - 3,600,000 per year

Job Summary:

We are seeking skilled and detail-oriented experienced FPGA Hardware and Software Engineer to join our engineering team with following competencies:

  • Own system architecture:
    Pick the right SoC/FPGA (e.g., Zynq/SoC-FPGA/RISC-V softcore), partition HW/SW, define interfaces, clocks, safety, redundancy, and boot/upgrade strategy.
  • HDL development:
    Write/maintain Verilog IP for sensor I/O, motor/servo control (PWM/PPM/S.Bus/DShot), comms (SPI/I²C/UART/CAN/MAVLink, Ethernet), high-rate DSP, timing & synchronization, and fault-tolerant logic.
  • Timing closure & verification:
    Create constraints (XDC/SDC), CDC handling, simulation (Questa/ModelSim/Verilator), unit tests/UVM where helpful, and on-hardware debug (ILA/SignalTap).
  • Firmware & control software:
    Bare-metal/RTOS or Linux on SoC (C/C++), drivers, HAL, DMA, interrupt & task design; integrate with ArduPilot/PX4 or a custom stack; implement control loops (PID), state estimation (e.g., EKF with IMU/GNSS/baro), and failsafe logic.
  • HIL & flight testing:
    Develop hardware-in-the-loop rigs, log/trace tools, automated bring-up scripts (Python/TCL), bench tests, and coordinate field tests with the flight team.
  • PCB design:
    Familiarity with ECAD tools like Altium and KiCAD for designing High-speed and mixed-signal boards, EMI/EMC, signal integrity, and sensor/actuator conditioning. Strong Ability to read and interpret schematics and datasheets for FPGA/SoCs.

What you'll bring

· Bachelor or Master's degree in Computer or Electrical Engineering or related field.

  • 2-3+ years building production FPGA/SoC systems (Xilinx/AMD or Intel/Altera), from architecture to timing closure.
  • Strong HDL (Verilog/SystemVerilog/VHDL) plus C/C++ for drivers/RTOS/Linux; Python/TCL for tooling.
  • Proven experience with sensor fusion / control systems (IMU, baro, GNSS), high-rate I/O, and deterministic timing.
  • Designed at least 2 to 3 complex custom PCB (power, high-speed buses, EMI/EMC) through manufacturing and bring-up.
  • Comfort with Vivado/Vitis / Quartus / Platform Designer, constraint management, CDC, and on-chip analyzers.
  • Hands-on HIL, bench instrumentation (scope, LA), and structured verification/test mindset.
  • Excellent technical writing; ability to turn ambiguous mission goals into clear, testable milestones.

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